1. Field of the Invention
The present invention relates to an error detecting/correcting code generating circuit and a method of controlling the error detecting/correcting code generating circuit.
2. Description of the Related Art
Japanese Laid-Open Patent Publication No. 6-324951 (corresponding to U.S. Pat. No. 5,313,475) discusses an error correcting code function and a parity interface scheme providing a translation capability between the error correcting code and parity protocols that are implemented for memory systems in personal computers.
Japanese Laid-Open Patent Publication No. 48-66334 discusses a parity check circuit for a data transfer system in which information is exchanged between a data processing unit and a memory unit having an ECC (Error Checking and Correction) code. The parity check circuit includes a code converting unit that performs code conversion between the ECC code and the parity check bit. It is discussed that the parity check bit can be directly calculated by an operating unit.